In the semiconductor industry the need for high pin count semiconductor devices is well known. Often, high pin count requirements lead to designs which are pad limited. A pad limited design is one where the overall die size is determined by the number of pads, as opposed to core limited design which is generally limited by the number of transistors needed to implement a specific device function. Typically, semiconductor devices have a single row of bond pads with a constant pad pitch. The constant pad pitch is determined by the worst case packaging requirements of the semiconductor device. For example, for high pin count packages, the pad pitch is generally determined by the pads located closest to the corner of the die. It is these pads that generally require a maximum pad pitch in order to allow bonding tools to function without interfering with adjacent bond wires. Therefore, this worst case pad pitch spacing is used to determine how many pads fit along an edge of a semiconductor die. The problem with using a single row of bond pads which are uniformly spaced is that it causes larger die sizes.
A prior art improvement over the traditional single row of bond pads having constant pad pitches is the use of constant wire pitches as taught in U.S. Pat. No. 5,498,767. A constant wire pitch device maintains a constant wire pitch, while the pad pitch between adjacent pads varies. Constant wire pitch is defined to be the orthogonal distance from the center of a bond pad to the adjacent wire. By maintaining a constant wire pitch across the edge of the die, the bond pads are no longer constrained by the use of worst case pad spacing. As a result, smaller die sizes are achievable. However, even with the use of constant wire pitch configuration, it is often common for a single row of pads to be the limiting factor of the overall device size.
It has been proposed in the industry to use dual rows of bond pads in order to further optimize die size for pad limited designs. One such proposal, put forth in U.S. Pat. No. 5,468,999 uses multiple rows of bond pads forming orthogonal sets of pads. FIG. 4 of the '999 patent, illustrates how the semiconductor device effectively has three identical rows of bond pads. In other words the second row is a virtual copy of the first row, offset from the first row in a perpendicular direction from the die edge. While this does provide some die size advantages, it is problematic in that the structure requires using multiple loop heights in order to avoid the shorting of wires. Using multiple loop heights in the packaging process increases complexity, cost, and decreases reliability of the overall semiconductor device. In addition, this patent requires bonding wires to be bonded in a generally orthogonal direction. As a result, it is primarily for use with low pin count devices.
Another dual row proposal is put forth in U.S. Pat. No. 5,195,237 uses multiple rows of bond pads. FIG. 3 of the '237 patent, and FIG. 5 of the '999 patent, it is illustrated how the semiconductor device effectively has two identical rows of bond pads that are non-overlapping, or have coincident edges, in a direction perpendicular to the die edge. However, this prior art teaches the individual pads having a constant pad pitch within each row. As a result, the number of total pads available is limited in that a worst case pad pitch must be maintained.
Therefore, a semiconductor device and method which is capable of decreasing the die size in pad limited layouts, and optimizing the number of bond pads for a given die size would be beneficial.